1. Technical Field
The present invention generally relates to a semiconductor device and, more particularly, to a semiconductor memory device having a silicon-on-insulator (SOI) structure and a method of manufacturing the same.
2. Description of Related Art
FIG. 1 is a circuit diagram of a conventional memory cell 70 used in a dynamic random access memory (DRAM). Memory cell 70 includes a storage capacitor 75 for storing charges and a MOS transfer transistor (or "transfer gate") 80 for controlling charge transfer. One end of the source-drain path of MOS transistor 80 is connected to bit line BL and the other end of the source-drain path of MOS transistor 80 is connected to a first electrode of capacitor 75. A second electrode of capacitor 75 is connected to a predetermined potential such as ground potential. The gate of MOS transistor 80 is connected to word line WL to which signals are applied for controlling the transfer of charges between storage capacitor 75 and bit line BL, thereby reading and writing data. While it is desirable to increase the integration density of memory cells on a memory chip by making the MOS transfer transistor and the storage capacitor smaller, the capacitor must nonetheless be large enough to store sufficient charge for ensuring that data is correctly read from and written to the memory cell. So-called trench capacitors have been developed to increase the capacitance of the storage capacitor while permitting the integration density of the memory cells to be increased.
As shown in FIG. 8, there is a semiconductor memory device including trench capacitors 81 in a first semiconductor substrate 90, a connecting diffusion region 83 between the trench capacitor 81 and source/drain region, and MOS transistor 86 disposed on the trench capacitor 81. This conventional art is described in Japanese Patent Disclosure (Kokai 6-104398, published on Apr. 15, 1994). Namely, this conventional device achieves high density DRAM using the capacitor disposed under the MOS transistor. There is only one gate 82 on the capacitor 81. Namely, there are a first semiconductor substrate 90, an n-type well layer 91 disposed on the substrate 90, a trench 92 disposed in the n-type well layer 91, a capacitor insulating film 93 disposed over the surface of the trench 92, a first polycrystalline silicon layer 94 filled up in the trench 92, a first SiO.sub.2 layer 95 deposited over the n-type well layer 91 and the first polycrystalline silicon layer 94, a second SiO.sub.2 layer 96 bonded to the first SiO.sub.2 layer 95, a second semiconductor substrate 97 disposed on the second SiO.sub.2 layer 96, a second polycrystalline silicon 98 performing as the connecting diffusion region 83, a thermal oxide layer 99 disposed on the second polycrystalline silicon layer 98, a gate oxide layer 100 disposed on the second semiconductor substrate 97, a gate polycrystalline silicon 101 disposed on the gate oxide layer 100, Si.sub.3 N.sub.4 layer 102 disposed on the gate polycrystalline silicon 101, a source/drain region diffused in the second semiconductor layer 97, and an n-type diffusion region for connecting the connecting diffusion region 83 and the source/drain region.